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Freescale Semiconductor /MK70F15WS /DDR /CR02

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Interpret as CR02

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TINIT0INITAREF 0RESERVED

Description

DDR Control Register 2

Fields

TINIT

Time Initialization
INITAREF

Initialization Auto-Refresh
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data